.css-1xsl8rf{width:100%;display:-webkit-box;display:-webkit-flex;display:-ms-flexbox;display:flex;-webkit-align-items:center;-webkit-box-align:center;-ms-flex-align:center;align-items:center;position:relative;overflow:hidden;background:var(--alert-bg);-webkit-padding-start:var(--chakra-space-4);padding-inline-start:var(--chakra-space-4);-webkit-padding-end:var(--chakra-space-4);padding-inline-end:var(--chakra-space-4);padding-top:var(--chakra-space-1);padding-bottom:var(--chakra-space-1);--alert-fg:var(--chakra-colors-orange-600);--alert-bg:var(--chakra-colors-orange-100);font-weight:var(--chakra-fontWeights-semibold);padding-left:var(--chakra-space-4);}.chakra-ui-dark .css-1xsl8rf:not([data-theme]),[data-theme=dark] .css-1xsl8rf:not([data-theme]),.css-1xsl8rf[data-theme=dark]{--alert-fg:var(--chakra-colors-orange-200);--alert-bg:rgba(251, 211, 141, 0.16);}@media screen and (min-width: 48em){.css-1xsl8rf{padding-left:var(--chakra-space-8);}}Please enable Javascript to use all features and improve your user experience.

Akitaka Yoshigoe

JAEA / JP

JAEA

Further involvements

11/10/2022
Poster Presentation
PP 252
Fabrication of stable and low leakage SiO₂/GaN MOS devices by sputter deposition of SiO₂ combined with post annealing processes
Characterization, Electronic devices